Design For Testability (DFT) is a specialisation in the SOC design cycle, which facilitates a design for detecting manufacturing defects. With increase in size & complexity of chips, facilitated by advancement of manufacturing technologies, it has evolved as a specialization in itself over a period of time. DFT Engineers, works on introducing various test structures as part of the design flow, to increase the testability of logic, pads, memories, interconnects. The course is designed and will be delivered by experts in DFT.